Fetch Execute Cycle
One of greatest example of von Neumann architecture is instruction cycle and also referred as fetch-execute cycle and in which CPU (Central Processing Unit) follows from all Booting of system until shut down of computer so as to process instruction. There are three stages in fetch execute cycle which are fetch stage, decode stage and execute stage. The instructional cycle is executed in a sequence manner in which each instruction is processed before starting of next instruction. In high tech systems, the instruction cycle is executed concurrently and sometimes in parallel manner too by an instruction pipeline. In this the next instruction is being processed before completion of previous instruction and it is due to broken up of cycle into separate steps.
The PC (Program Counter) is a special register which have ability to hold memory address of upcoming instruction which is to be executed. In the fetch stage, the address stored in PC is copied to MAR (Memory Address Register) and after that PC is incremented as it points to memory address of upcoming instruction. Further, the CPU takes instruction from memory address described by MAR and copies into MDR (Memory Data Register). The MDR acts as a two way register as it holds the data from memory or from data waiting to be stored in memory. At last, the instruction in MDR is copied to CIR (Current Instruction Register) which holds instruction from fetched memory temporarily. During the decode stage, the control Unit decodes instruction in CIR and CU sends signals to other components of CPU.
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Levels of fetch executive cycle
The cycle begins as the power is applied to system by an initial PC value that is predefined by system architecture. Mainly, this instruction points to a set of instructions in ROM (Read Only Memory) which starts process of booting of operating system. This will help students in getting aware about concepts of fetch execute cycle.
The first step in fetch execute cycle is to capture instruction from RAM and this memory is assigned to processor by various registers and units.
- The CPU transmits or send contents of PC to MAR and send read command to control bus.
- The memory returns the data stored at memory location which is indicated by PC on data bus.
- CPU copies data from data bus and pate into MDR.
- In a fraction of seconds, the CPU copies data from MDR to instruction register for purpose of instruction decoding.
- The PC is incremented so as it can point to next instruction. This step helps in preparing of CPU for next cycle.
The decoding process helps in allowing CPU to determine what instructions are to be performed so that CPU can instruct how many operands it is needed to fetch so as to perform instructions. The code fetched from the memory are decoded for next step and move to appropriate register. The process of decoding is typically performed by binary decoders in Control Unit. There are various instructions and can never be sure which instruction belongs to which execution unit but with help of decoder, this issue sorts out. As decoderis responsible for taking instruction and decoding by assigning to right execution unit so as to complete instruction cycle.
Reading effective address
This step helps in evaluating type of operation to be performed. If the operation is memory operation, the system checks whether it is a direct or indirect memory operation.
- Direct memory Operation– Nothing is to be done.
- Indirect Memory Operation – Effective address is read from memory.
If it is resister of input/output instruction, system checks its type and executes operation.
The CPU sends the decoded instructions in a set of control signals to corresponding computer components. In case of instruction uses arithmetic and logic, ALU is used. This is the stage which is useful from the point of view of user and everything else is required to happen automatically. No two instructioncan be resolved in a same manner as their way of utilising hardware depends on their function. In system terminology, there are four types of instructions which are usually present and can be beneficial for students.
- Arithmetic instruction -This type of instruction involves mathematical as well as logical operations. They are usually solved by ALU (Arithmetic Logical Units).
- Bit movement instruction-This type of instruction involves manipulation of order of bits in which data is stored.
- Jump instructions – In this type of instruction, the code is used recursively as the value for next program counter is changed.
- Instruction to memory-These types of instruction involves processor writing along with reading information from memory of system. One completion of cycle, a new instruction gets fetched and this cycle continues.
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Working of Control Unit in fetch execute cycle
- Th control unit is responsible for controlling external and internal transmission of data in processor. In addition to that, it is also responsible for controlling of movement of data in several subunits involved.
- There is various stage of capture stage of instruction cycle which are considered crucial part of hardware. Moreover, the hardware is also known as processor's front end or control unit.
- Control Unit is responsible for interpreting different instructions as well as transmits to various execution units.
- It also communicates data for instruction to several ALUand to execution units at work.
- It acts as an important part of process which captures and decodes instruction for purpose of execution. In addition to that, it is also responsible for writing results on address of RAM and on registers too.
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Most searched FAQs
Q1. What are the stages of fetch execute cycle?
Ans. This cycle is a key feature of von Neumann architecture and consist of three stages fetch, execute and decode. In this, the data is stored from memory and by the instructions it gets transmitted to register in order to perform task. Each instruction is being processed before starting of new instruction.
Q2. What happens at the fetch stage?
Ans. An address is being used to fetch instructions from memory and this address is copied to memory address register. The instruction is fetched from memory address which is currently stored in program counter and stores in instruction register. In the ending stage of fetch operation, PC points to next instruction that is read at next cycle.